hi,
just for the reference, short discussion on low end SRX design:
http://forums.juniper.net/t5/Tech-Cafe-Current-Event/SRX-for-branch-office-vs-SRX-for-data-center-SRX-Series-Services/m-p/62571#M167
And some logs:
SRX100
SRX100> show system boot-messages
[...]
FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs
[...]
cpu0 on motherboard
: CAVIUM's Octeon CPU Rev. 0.1 with no FPU implemented
L1 Cache: I size 32kb(128 line), D size 8kb(128 line), sixty four way.
L2 Cache: Size 128kb, ? way
[...]
SMP: AP CPU #1 Launched!
SRX240
SRX240> show system boot-messages
[...]
FreeBSD/SMP: Multiprocessor System Detected: 4 CPUs
[...]
cpu0 on motherboard
: CAVIUM's Octeon CPU Rev. 0.8 with no FPU implemented
L1 Cache: I size 32kb(128 line), D size 8kb(128 line), sixty four way.
L2 Cache: Size 128kb, ? way
[...]
SMP: AP CPU #1 Launched!
SMP: AP CPU #2 Launched!
SMP: AP CPU #3 Launched!
SRX650
SRX650> show system boot-messages
[...]
FreeBSD/SMP: Multiprocessor System Detected: 12 CPUs
[...]
cpu0 on motherboard
: CAVIUM's Octeon CPU Rev. 0.9 with no FPU implemented
L1 Cache: I size 32kb(128 line), D size 8kb(128 line), sixty four way.
L2 Cache: Size 128kb, ? way
[...]
SMP: AP CPU #1 Launched!
SMP: AP CPU #3 Launched!
SMP: AP CPU #4 Launched!
SMP: AP CPU #8 Launched!
SMP: AP CPU #9 Launched!
SMP: AP CPU #7 Launched!
SMP: AP CPU #5 Launched!
SMP: AP CPU #10 Launched!
SMP: AP CPU #11 Launched!
SMP: AP CPU #2 Launched!
SMP: AP CPU #6 Launched!
No logs for SRX210/220 here.
I don't think we will get more details on SRX design than 'one core is used for control plane functionality and the rest of the cores for data plane'
jtb