SRX

We're working on building a community zenoss zenpack for the srx series, specially the srx 240h in a cluster.  We have cpu and routing engine cpu being graphed (amount other metrics).

I've read these have a quad core octeon processor in them.  So I'm wondering what different planes/engines are in use and how the quad core octeons are utilized.  Any help in understanding how the hardware fits into the junos architecture on the devices would be greatly appreciated.

this is product internal design, might not be sharable by juniper

regards

If memory serves the SRX100, SRX210, SRX220, and SRX240 use dual-core processors and the SRX650 uses a quad-core processor.  As rasmus mentioned this is likely to be under NDA and unfortunately I can't remember the third party source I gathered this information from.

mawr

hi, 

just for the reference, short discussion on low end SRX design:

http://forums.juniper.net/t5/Tech-Cafe-Current-Event/SRX-for-branch-office-vs-SRX-for-data-center-SRX-Series-Services/m-p/62571#M167

And some logs:

SRX100

SRX100> show system boot-messages    
[...]
FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs
[...]
cpu0 on motherboard
: CAVIUM's Octeon CPU Rev. 0.1 with no FPU implemented
        L1 Cache: I size 32kb(128 line), D size 8kb(128 line), sixty four way.
        L2 Cache: Size 128kb, ? way
[...]
SMP: AP CPU #1 Launched!

SRX240

SRX240> show system boot-messages                    
[...]
FreeBSD/SMP: Multiprocessor System Detected: 4 CPUs
[...]
cpu0 on motherboard
: CAVIUM's Octeon CPU Rev. 0.8 with no FPU implemented
        L1 Cache: I size 32kb(128 line), D size 8kb(128 line), sixty four way.
        L2 Cache: Size 128kb, ? way
[...]
SMP: AP CPU #1 Launched!
SMP: AP CPU #2 Launched!
SMP: AP CPU #3 Launched!

SRX650

SRX650> show system boot-messages    
[...]
FreeBSD/SMP: Multiprocessor System Detected: 12 CPUs
[...]
cpu0 on motherboard
: CAVIUM's Octeon CPU Rev. 0.9 with no FPU implemented
        L1 Cache: I size 32kb(128 line), D size 8kb(128 line), sixty four way.
        L2 Cache: Size 128kb, ? way
[...]
SMP: AP CPU #1 Launched!
SMP: AP CPU #3 Launched!
SMP: AP CPU #4 Launched!
SMP: AP CPU #8 Launched!
SMP: AP CPU #9 Launched!
SMP: AP CPU #7 Launched!
SMP: AP CPU #5 Launched!
SMP: AP CPU #10 Launched!
SMP: AP CPU #11 Launched!
SMP: AP CPU #2 Launched!
SMP: AP CPU #6 Launched!

No logs for SRX210/220 here.

I don't think we will get more details on SRX design than  'one core is used for control plane functionality and the rest of the cores for data plane'

jtb

SRX220

cpu0 on motherboard
: CAVIUM's OCTEON 5020 CPU Rev. 0.1 with no FPU implemented
        L1 Cache: I size 32kb(128 line), D size 8kb(128 line), sixty four way.
        L2 Cache: Size 128kb, 8 way

FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs

Timecounter "mips" frequency 700000000 Hz quality 0

SRX210> show system boot-messages

[...]

FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs
[...]

cpu0 on motherboard
: CAVIUM's Octeon CPU Rev. 0.1 with no FPU implemented
        L1 Cache: I size 32kb(128 line), D size 8kb(128 line), sixty four way.
        L2 Cache: Size 128kb, ? way

[...]

SMP: AP CPU #1 Launched!

Now the only one we're missing is the SRX210 'Enhanced' with faster CPU (SRX210BE & SRX210HE)...

Out of curiosity, did you get anywhere with your zenpack?  I run zenoss 3.1, and the older stuff for 2.x seems to not work well.. (and is fairly limited).