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The term VOQ has been over-used and evolved over time.  So while all routing vendors claim a VOQ architecture, they all differ in the actual implementation. These differences are quite substantial and having meaningful impcact on the performance and cost of the system.  Much of this evolution has occurred to try and eliminate shortcoming in their systems, such as HOLB problems.


This part will go thru various VOA implementations and illustrate their strengths and weaknesses.


This is the second part of a 3 part series discussing how VOQ architectures differ from one another and how they evolved over time.  In this part, we will duscuss about the fundamental backplane components and how the need for VOQ came about.


This will be a multi-part BLOG that describes the evolution of VOQ and will attempt to explain why not all VOQ implementations are equal.  It will NOT attempt to review all possible VOQ implementations.  But instead try to explain how it evolved and the motivations that drove it.



BTW, please feel free to offer constructive criticisms


Trio Packet Processing – Memory System

by Juniper Employee ‎08-26-2016 10:00 AM - edited ‎08-30-2016 03:13 PM


The control-plane SW for a Trio system creates an executable data structure based on the router configuration and on connectivity information from protocols such as BGP.


The Packet Processing Engine (PPE) used in the Trio architecture is a VLIW (Very Long Instruction Word), multi-threaded micro-coded engine core. Each micro-instruction controls multiple 32-bit ALUs, operand and result selection, complex multi-way branching, and some miscellaneous functions.

In this blog, I’ll focus on some of the aspects of the PPE that make it particularly well-suited to handle packet processing in a router/switch.


Trio Packet Processing – Overview

by Juniper Employee ‎08-12-2016 11:22 AM - edited ‎08-12-2016 01:51 PM

Trio Processing.png

Juniper’s MX series edge and aggregation routers and switches have been based on Trio architecture chipsets for the last six years.  The Trio architecture includes a packet processing model that is fully programmable to provide flexibility, and also provides high performance. This architecture has had longevity – the Juniper Silicon Development team is currently working on the fourth generation Trio architecture chipset.




You Truly Get What You Pay with Power Sequencing on PTX

by Juniper Employee ‎07-07-2016 01:27 PM - edited ‎07-07-2016 01:33 PM

If you take a first class flight, you can enjoy many privileges: preferential check-in, superb meal service, comfortable seating, the crew’s dedicated attention, you know the drill. These privileges separate first class from economy class. But if the flight is delayed or cancelled, you are equally out of luck, regardless of the ticket. In situations like this, there is no service differentiation!


In networking, there is also a differentiation among various customers and their traffic, called Class of Service (COS). But if the whole card is down due to some power supply failure on the router or switch, same as airline's passengers, all traffic, whether high or low COS, will be stopped and lost. Again, no service differentiation.


On PTX, an innovation is introduced to solve this problem. This innovation is called power sequencing—with it, not only does the traffic on a port have service differentiation, but so do the cards on a chassis during power-on and at power failure.


PTX Deserves an Oscar Award

by Juniper Employee ‎06-08-2016 03:22 PM - edited ‎06-09-2016 10:19 AM

Still remember when former vice president Al Gore’s movie, “An Inconvenient Truth”, won an Oscar for best documentary? The movie raised the general public’s awareness of the threat of global warming.  If there were an Oscar in the networking industry, Juniper’s PTX-series platform certainly deserves one for its “Go Green” and for preventing global warming with several innovations in cooling and energy consumption:

  • Linear cooling algorithm
  • Multi-zone cooling
  • Section cooling
  • Multi-sensor temperature monitoring

Intelligent Power Management 1.0

by Juniper Employee ‎12-29-2015 02:55 PM - edited ‎12-29-2015 03:01 PM

I’ve been with Juniper networks for many years, far more than I care to admit. Over that time a few things have never changed: routers keep getting faster and total power consumption rises unabated. Although the power required per unit bandwidth (power efficiency) continues to improve the growth of aggregate power requirements put a heavy strain on the power infrastructure of the service provider and represents financial expenditure.

Intelligent power management is needed to limit the power growth and resulting impact on the power infrastructure.



Comparing Apples to Oranges: The Meaning of Bandwidth.

by Juniper Employee ‎05-15-2015 01:35 PM - edited ‎06-04-2015 04:42 PM

Part of my role in the Juniper Networks Routing platform team is to review and decipher marketing announcements from our competitors. Just recently I stumbled upon one such announcement which inspired me to create this blog and share with you my observations on bandwidth [BW] measurements. My objective is to bring awareness to customers and sales engineers of how to correctly understand and approach network BW capacity. The following blog represents my personal opinion and not necessarily that of Juniper Networks.

Let’s get going…


The marketing announcement that sparked my interest in this topic was an advertisement publicizing “the industry’s first 2 Tbps line card.” My initial reaction was something like: Really? I hate to be the bearer of bad news, but this is a little late. The new benchmark is 3 Tbps since Juniper’s release of the PTX FPC3 on March 11th . However, I decided to sit down, take a sip of espresso, and try to understand the methodology behind this announcement.