MX Series routers are available in a variety of configurations with robust features, including options that provide the level and granularity of the quality-of-service (QoS) support needed in your network. The MX Series hardware options currently include five models of Modular Port Concentrators (MPCs), using several different Modular Interface Cards (MICs), and three models of Dense Port Concentrators (DPCs). The MPCs and DPCs provide varying degrees of QoS support.
The DPCs (DPCE-X, DPCE-R, and DPCE-Q) each provide multiple physical interfaces and Packet Forwarding Engines on a single board that performs packet processing and forwarding. Each Packet Forwarding Engine consists of one I-chip for Layer 3 processing and one network processor for Layer 2. DPCE-Qs offer enhanced queuing capabilities and the QoS features of weighted round robin (WRR), random early detection (RED), and weighted random early detection (WRED).
To ramp up on DPC overview information, click: MX Series Interface Module Reference
This article provides answers to the most common questions about DPCs on MX Series routers.
- How many Layer 3 and Layer 2 policers are supported on Juniper Networks MX Series devices?
- Are peak information rate (PIR) and committed information rate (CIR) supported at the queue level on...
- Is it possible to use a common QoS scheduler on a traffic-class group comprised of an aggregate of m...
- Is hierarchical QoS per VLAN supported on aggregated Ethernet (AE) interfaces?
- What are the differences between the CoS traffic-manager options on the MX Series?
- How is the shaping rate calculated on the Enhanced Queuing DPCs (DPCE-R-Qs)?
- What is the queuing buffer size on MX Series DPCs?
- Are fine-grained queuing capabilities supported on Enhanced Queuing DPCs (DPCE-R-Q)?
- What are the QoS properties of the DPCE-R and DPCE-Q line cards?
- What are the QoS properties of the DPCE-R line cards?
- What are the QoS properties of the Enhanced Queuing DPCs (DPCE-R-Q)?
- Is DiffServ code point (DSCP) classification of MPLS-tagged packets supported on the I-chip-based DP...