GRE tunnels in MX series

01.23.12   |  
‎01-23-2012 04:31 PM

Hi, I need to know how many GRE tunnels are supported in the MX family, I find that this devices can support until JUNOS release 10 and after, but I cant find the maximun to this tunnels.


Re: GRE tunnels in MX series

01.24.12   |  
‎01-24-2012 12:08 AM

There is no limitation on the amount of GRE tunnels on the MX-series. When using MPC linecards (based on Trio chipset) the tunneling can be performed in-line on the Trio chip and you don't require a dedicated ASIC anymore. 


The limitation is on throughput, the chipset offers 30Gbps of throughput linerate. The tunneling is done in hardware and therefore is not limited, except to the chip limits.

Triple CCIE #21946 (R&S / Service Provider / Storage), JNCIE-SP #851, Technical Consultant at Telindus-ISIT

Re: GRE tunnels in MX series

01.24.12   |  
‎01-24-2012 06:35 AM

Thanks for your answer, but do you tell me in with site (paper, KB), I can support this answer, I need to support this with any document or link with my client.


Thanks for your help.


Re: GRE tunnels in MX series

01.26.12   |  
‎01-26-2012 05:33 AM

Can help me with a document that support that only apply the Troughput when we can create GRE tunnels?? I need to suppor this with a KB, Release note or some specific document


Re: GRE tunnels in MX series

[ Edited ]
02.06.12   |  
‎02-06-2012 05:01 PM

  • Mentions the "inline" nature of the GRE service on the Trio chipset. (pg 2 under trio chipset) 

  • Describes the need to limit the services by bandwidth, not by number of tunnels/services (pg 7-8)

  • Describes a testing environment with 1000 GRE tunnels
Ben Boyd
Sr. Solutions Architect
Integration Partners (
Twitter - @ozark46